Patent Number: 6,167,499

Title: Memory space compression technique for a sequentially accessible memory

Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.

Inventors: Letham; Lawrence (Chandler, AZ)

Assignee: VLSI Technology, Inc.

International Classification: G11C 7/10 (20060101); G11C 8/04 (20060101); G11C 19/00 (20060101); G06F 007/00 ()

Expiration Date: 12/26/2017