Patent Number: 6,167,503

Title: Register and instruction controller for superscalar processor

Abstract: In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.

Inventors: Jouppi; Norman P. (Palo Alto, CA)

Assignee: Compaq Computer Corporation

International Classification: G06F 9/30 (20060101); G06F 9/38 (20060101); G06F 009/22 ()

Expiration Date: 12/26/2017