Patent Number: 6,167,507

Title: Apparatus and method for floating point exchange dispatch with reduced latency

Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit. The floating point instruction unit receives the exchange register information, exchanges the top-of-stack with the register specified by the exchange register information and then performs the floating point operation. In the above manner, two floating point operations may be executed in a single clock cycle.

Inventors: Mahalingaiah; Rupaka (Austin, TX), Miller; Paul K. (McKinney, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 9/30 (20060101); G06F 9/318 (20060101); G06F 9/38 (20060101); G06F 9/315 (20060101); G06F 009/38 ()

Expiration Date: 12/26/2017