Patent Number: 6,167,508

Title: Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency

Abstract: Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter. Addition speed increase may be achieved by dividing the register scoreboard logic into odd and even register scoreboard arrays on either side of the arbiter.

Inventors: Farrell; James A. (Harvard, MA), Gieseke; Bruce A. (San Jose, CA)

Assignee: Compaq Computer Corporation

International Classification: G06F 9/30 (20060101); G06F 9/38 (20060101); G06F 009/38 ()

Expiration Date: 12/26/2017