Patent Number: 6,167,510

Title: Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache

Abstract: An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor.

Inventors: Tran; Thang M. (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 12/08 (20060101); G06F 9/38 (20060101); G06F 015/00 ()

Expiration Date: 12/26/2017