Patent Number: 6,167,526

Title: Method and apparatus for synchronizing a decoder circuit with a phase-encoded data signal in a data storage device

Abstract: An invention for intelligently adjusting the timing of generation of a series of detection windows to maintain synchronization with the occurrence of data pulses within a stream of phase-encoded binary data is disclosed. In an embodiment of the present invention, thresholding logic is added to a limited response self-clocking decode phased locked loop to achieve a more robust data detection method and system, which is less susceptible and sensitive to noise error. In one embodiment of the system, an up/down counter is used to count to occurrence of late and early data pulses within their respective detection window, with the timing of the generated series of detection windows being adjusted when the value of this counter exceeds an upper or lower predetermined threshold value.

Inventors: Carlson; Lance Robert (Niwot, CO)

Assignee: Adaptec, Inc.

International Classification: G11B 20/10 (20060101); G06F 3/06 (20060101); H04L 7/08 (20060101); G06F 013/42 ()

Expiration Date: 12/26/2017