Patent Number: 6,167,528

Title: Programmably timed storage element for integrated circuit input/output

Abstract: A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate programmable skew buffer. The programmable skew buffer includes a clocked storage element that receives data from an input pin and outputs data to the memory array in the memory device when optimizing the input timing of the memory device, or receives data from the memory array in the memory device and outputs data to an output pin when optimizing the output timing of the memory device. The programmable skew buffer also includes a programmable delay circuit which generates one of a plurality of clock signals wherein each signal represents a delayed version of the system clock. The clock signal generated by the programmable delay circuit provides the input clock signal into the clocked storage element such that data is clocked into the clocked storage element in response to the input clock signal.

Inventors: Arcoleo; Mathew (San Jose, CA)

Assignee: Cypress Semiconductor

International Classification: G06F 1/10 (20060101); G11C 7/22 (20060101); G11C 7/10 (20060101); G11C 7/00 (20060101); G11C 11/417 (20060101); G06F 001/04 ()

Expiration Date: 12/26/2017