Patent Number: 6,167,529

Title: Instruction dependent clock scheme

Abstract: A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.

Inventors: Dalvi; Vishram P. (Folsom, CA)

Assignee: Intel Corporation

International Classification: G06F 9/38 (20060101); G06F 001/04 ()

Expiration Date: 12/26/2017