Patent Number: 6,167,540

Title: Semiconductor memory device and redundant address selection method therefor

Abstract: In a semiconductor memory device including a normal memory constituted by a plurality of normal memory cells and a redundant memory constituted by a plurality of redundant memory cells, a predecoder decodes an address signal and outputs a corresponding address selection signal to an array interconnection. A normal address decoder selects a normal memory cell in the normal memory on the basis of an address selection signal from the predecoder. A redundant address decoder selects a redundant memory cell in the redundant memory on the basis of an address selection signal from the predecoder. When a defective normal memory cell in the normal memory is designated by the address signal, a control unit outputs, to the predecoder, an inactivating signal for inactivating the normal memory and a redundant memory cell selection signal for selecting the redundant memory cell in the redundant memory in place of the defective normal memory cell in the normal memory. The predecoder outputs an address selection signal corresponding to the redundant memory cell selection signal from the control unit to the array interconnection on the basis of the inactivating signal and the redundant memory cell selection signal from the control unit.

Inventors: Azuma; Mitsuhiro (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G11C 29/00 (20060101); G11C 029/00 (); G11C 007/00 ()

Expiration Date: 12/26/2017