Patent Number: 6,167,542

Title: Arrangement for fault detection in circuit interconnections

Abstract: Testing time of interconnections is reducted by splitting up the collection of connection paths to be tested into two or more groups. A set of test vectors, which is applied to each of the groups concurrently, is arranged to insure that the two adjacent connections that are assigned to different groups are not tested concurrently. The user can select the number of groups, and the number of connection paths within each group (which need not be the same for all groups). The disclosed algorithm increases the number of connection paths that are tested with each concatenated test vector, and consequently the number of required test vectors is reduced.

Inventors: Chakraborty; Tapan Jyoti (West Windsor, NJ), VanTreuren; Bradford Gene (Lambertville, NJ)

Assignee: Lucent Technologies

International Classification: G01R 31/3183 (20060101); G01R 31/28 (20060101); G01R 31/319 (20060101); G11C 029/00 ()

Expiration Date: 12/26/2017