Patent Number: 6,167,543

Title: Memory test mode circuit

Abstract: A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input pins. Each of the non-standard signal levels are detected by a separate signal level detection circuit. A predetermined combination of input signals then provides a control signal which sets the integrated-circuit into a predetermined test mode. A non-standard Vcc/2 signal level is detected by determining that it is above a predetermined low threshold level of 1/4 Vcc and below a predetermined high threshold level of 3/4 Vcc. Additional non-standard input signal levels which are close to Vcc and Vss are also used. A chip enable (CEX) signal is used to enable the signal level detection circuit when a chip is enabled. A delay circuit is serially coupled to the output terminal of the signal level detection circuit to require the input signals to have a predetermined minimum time duration.

Inventors: Callahan; John M. (San Ramon, CA)

Assignee: NanoAmp Solutions, Inc.

International Classification: G11C 29/04 (20060101); G11C 29/46 (20060101); G11C 029/00 ()

Expiration Date: 12/26/2017