Patent Number: 6,167,554

Title: Combinational logic circuit, its design method and integrated circuit device

Abstract: A combinational logic circuit having at least one primary input terminal and at least one primary output terminal comprises a plurality of VDDH gates having an input node and an output node and operated by a standard operating voltage and a plurality of VDDL gates having an input node and output node and operated by an operating voltage which is lower than the standard operating voltage. At least one of the VDDH gates is multiple input gate. An output node of the VDDH gate or primary input terminal operated by the standard operating voltage is connected to at least one of the input nodes of the multiple input gate. The VDDL gate or the primary output terminal operated at the operating voltage which is lower than the standard operating voltage is connected to at least one of the other input nodes of the multiple input gate through a level converter.

Inventors: Ishikawa; Takashi (Tokyo, JP), Usami; Kimiyoshi (Tokyo, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G06F 17/50 (20060101); H03K 19/00 (20060101); H03K 19/0185 (20060101); G06F 017/50 ()

Expiration Date: 12/26/2013