Patent Number: 6,167,557

Title: Method and apparatus for logic synthesis employing size independent timing optimization

Abstract: Size independent timing optimization is performed on an initial circuit design using gain based models for logic cell types. A component library containing various logic elements in a plurality of sizes is provided and a single gain based model for each logic element (cell type) is created therefrom. Initial conditions for gain and delay are then established for each cell type. Gain based optimization, which is size independent, is then performed on the initial circuit design. The optimized size independent solution is then transformed into a realizable discrete circuit solution.

Inventors: Kudva; Prabhakarn N. (Danbury, CT), Kung; David S. (Chappaqua, NY), Stok; Leon (Mount Kisco, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 12/26/2017