Patent Number: 6,167,558

Title: Method for tolerating defective logic blocks in programmable logic devices

Abstract: A fault tolerance method for FPGAs featuring interconnect resources made up of wiring segments that are programmably coupled to two or more configurable logic blocks (CLBs) through connection switches. In accordance with a first embodiment, one of the wiring segments is designated as being reserved for each CLB. During routing, a wiring segment is assigned to a signal path only if the signal path is not associated with signal transmission to or from the CLB to which the wiring segment is reserved. In accordance with a second embodiment, one or more connection switches are designated as reserved switches for each horizontal segment. During routing, the reserved switches are not used to route signal paths. Fault tolerance is then performed by shifting the logic portion assigned to a defective CLB and/or the associated switch configuration data along its row towards a spare CLB located at the end of the row. Accordingly, the signal path is shifted away from the defective CLB to a functioning CLB without changing the wiring segment assigned to the signal path, and, therefore, without changing the timing specification of the signal path. If the wiring segments are staggered such that adjacent wiring segments are selectively coupled to different groups of logic blocks in the same row, then fault tolerance adjustments do not introduce significant restrictions on interconnect resource allocation.

Inventors: Trimberger; Stephen M. (San Jose, CA)

Assignee: Xilinx, Inc.

International Classification: G01R 31/3185 (20060101); G01R 31/28 (20060101); G06F 017/50 ()

Expiration Date: 12/26/2017