Patent Number: 6,169,684

Title: Semiconductor memory device

Abstract: A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

Inventors: Takahashi; Kazunari (Shiga, JP), Agata; Masashi (Osaka, JP), Kuroda; Naoki (Kyoto, JP), Fujita; Tsutomu (Osaka, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 12/08 (20060101); G11C 11/409 (20060101); G11C 11/00 (20060101); G11C 11/4097 (20060101); G11C 015/00 ()

Expiration Date: 01/02/2018