Patent Number: 6,169,689

Title: MTJ stacked cell memory sensing method and apparatus

Abstract: Apparatus and method of reading the state of each cell in a stacked memory comprising stacks of cells in an addressable array with each stack including MTJ memory cells stacked together with current terminals connected in series, and including a first and second current terminals coupled through an electronic switch to a current source. Each stack includes 2.sup.n levels of memory. A voltage drop across an addressed stack is sensed. Reference voltages equal to the 2.sup.n memory levels are provided and the sensed voltage drop is compared to the reference voltages to determine the memory level in the addressed stack. Encoding apparatus is used to convert the voltage drop to a digital output signal.

Inventors: Naji; Peter K. (Phoenix, AZ)

Assignee: Motorola, Inc.

International Classification: G11C 11/02 (20060101); G11C 11/56 (20060101); G11C 11/15 (20060101); G11C 009/07 ()

Expiration Date: 01/02/2018