Patent Number: 6,169,968

Title: Apparatus and method for estimating performance integrated circuit

Abstract: The invention provides an apparatus and a method for accurately and rapidly estimating a performance of an integrated circuit in the design at a register transfer level. A parsing member converts an HDL description of the integrated circuit at the register transfer level into a representation by using parse trees, and a parse tree allocation member allocates elements of the integrated circuit to respective nodes of the parse trees. A trade-off estimation member predicts a minimum area which can satisfy a timing constraint by applying estimation models stored in an estimation library to the respective elements of the integrated circuit represented by using connections between the elements, and by appropriately changing application of driver models stored in a driver library. A performance candidate list generation part generates, by changing the application of the driver models, a list of performance candidates each represented as a group of {area, delay, driving ability} with regard to each element on the path not satisfying the timing constraint. A performance candidate selection part selects a performance candidate which can satisfy the timing constraint and can minimize the area increase of the integrated circuit.

Inventors: Kabuo; Chie (Kyoto, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 01/02/2018