Patent Number: 6,170,035

Title: Dynamic random access memory (DRAM) having variable configuration for data processing system and corresponding expansion support for the interleaved-block configuration thereof

Abstract: Dynamic random access memory with variable configuration depending on the number and capacity of standard memory modules, of DIMM type plugged into a first plurality of slots of a memory motherboard comprising a control unit, into which it is possible to plug, into the first plurality of slots, in substitution for the memory modules, expansion supports, in turn provided with a second plurality of slots for the insertion of standard memory modules of DIMM type, and of column address latch registers each associated with a slot of the second plurality and thereby to support and allow the configurability and operability of interleaved-block memory, and access cycles, with partial time overlap, without renouncing the use of commercially available DIMM memory modules and without burdening the basic memory configuration with all the overheads required to support the interleaved-block configuration.

Inventors: Gianellini; Marco (Milan, IT), Lazzari; Angelo (Pavia, IT)

Assignee: Bull HN Information Systems Italia S.p.A.

International Classification: G11C 7/00 (20060101); G11C 5/00 (20060101); G06F 012/00 ()

Expiration Date: 01/02/2018