Patent Number: 6,170,039

Title: Memory controller for interchanging memory against memory error in interleave memory system

Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.

Inventors: Kishida; Yuichi (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G06F 11/20 (20060101); G06F 12/06 (20060101); G06F 012/00 (); G06F 012/06 ()

Expiration Date: 01/02/2018