Patent Number: 6,170,046

Title: Accessing a memory system via a data or address bus that provides access to more than one part

Abstract: In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data. When simultaneous read accesses are desired to read data stored in one of the memories, the read accesses can be performed instead to different memories that are mirror images of each other. When any memory is written, all the memories of the same set are written with the same data.

Inventors: Joffe; Alexander (Palo Alto, CA), Birger; Ari (Sunnyvale, CA)

Assignee: MMC Networks, Inc.

International Classification: G11C 7/10 (20060101); G06F 012/02 ()

Expiration Date: 01/02/2018