Patent Number: 6,170,052

Title: Method and apparatus for implementing predicated sequences in a processor with renaming

Abstract: Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs of conditional instructions update a destination register regardless of the truth or falsity of the predicate. The destination register is renamed to a new physical location. In this manner, register renaming can be used with predicate sequences to gain performance efficiencies and to overcome limitations of the prior attempted approaches.

Inventors: Morrison; Michael J. (Santa Clara, CA)

Assignee: Intel Corporation

International Classification: G06F 9/32 (20060101); G06F 9/30 (20060101); G06F 9/38 (20060101); G06F 021/06 ()

Expiration Date: 01/02/2018