Patent Number: 6,170,054

Title: Method and apparatus for predicting target addresses for return from subroutine instructions utilizing a return address cache

Abstract: A method of operation in a microprocessor is provided. A return address cache (RAC) is initialized. The RAC includes a portion to store predicted subroutine return addresses (PSRA) and first and second corresponding cache portions to store retired most recently updated (RMRU) ages of the PSRA and speculative most recently updated (SMRU) ages of the PSRA respectively. A PSRA is stored in a portion of the RAC corresponding to a first SMRU age and the SMRU ages are incremented responsive to prediction of a call instruction. A PSRA is read from a portion of the RAC corresponding to a second SMRU age and the SMRU ages are decremented responsive to prediction of a return instruction. Also a microprocessor that includes a return address cache (RAC) is provided. The RAC includes first and second tag portions to store retired most recently updated (RMRU) ages and speculative most recently updated (SMRU) ages respectively. The RAC also includes a data portion to store predicted subroutine addresses (PSRA). The RAC also includes a control logic to cause the RMRU ages to be copied onto corresponding SMRU ages responsive to detection of a branch misprediction.

Inventors: Poplingher; Mitchell Alexander (Palo Alto, CA)

Assignee: Intel Corporation

International Classification: G06F 9/42 (20060101); G06F 9/40 (20060101); G06F 009/42 ()

Expiration Date: 01/02/2018