Patent Number: 6,170,068

Title: System and method for preserving the state of a device across a reset event

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.

Inventors: Liddell; David C. (Gosforth, GB), Williams; Emrys J. (Bow Brickhill, GB)

Assignee: Sun Microsystems, Inc.

International Classification: G06F 11/00 (20060101); G05B 9/02 (20060101); G06F 1/26 (20060101); G06F 13/00 (20060101); H03K 19/007 (20060101); H03K 19/003 (20060101); H02H 3/05 (20060101); G06F 011/00 ()

Expiration Date: 01/02/2018