Patent Number: 6,170,072

Title: Logic circuit verification apparatus and method for semiconductor integrated circuit

Abstract: There is constituted a logic circuit verification apparatus designed for checking a semiconductor integrated circuit including a core and a new circuit. The core has a internal circuit in which logic and timing have already been verified. The apparatus is provided with a section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit. The apparatus is also provided with a section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit. At the time of simulation, predetermined processing is performed solely with regard to the extracted cells.

Inventors: Moriguchi; Yasuo (Tokyo, JP), Inoshita; Toshinori (Tokyo, JP), Inoue; Yoshio (Tokyo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G01R 31/30 (20060101); G01R 31/28 (20060101); G01R 031/28 ()

Expiration Date: 01/02/2018