Patent Number: 6,170,080

Title: Method and system for floorplanning a circuit design at a high level of abstraction

Abstract: A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.

Inventors: Ginetti; Arnold (Antibes, FR), Tarroux; Gerrard (Villeneuve Loubet, FR), Silve; Francois (Mouamf-Sartoux, FR), Fernandes; Jean-Michel (Antibes, FR), Troin; Philippe (Milpitas, CA), Giomi; Jean-Charles (Woodside, CA)

Assignee: VLSI Technology, Inc.

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 01/02/2018