Patent Number: 6,250,821

Title: Method and apparatus for processing branch instructions in an instruction buffer

Abstract: An instruction buffer includes a shift register and control logic. The shift register includes M storage elements to store a maximum of M instructions before they are issued to an instruction decoder. The control logic issues instructions from the shift register to the instruction decoder and shifts remaining instructions into vacant storage elements in the shift register. When the control logic detects that N consecutive storage elements in the shift register are vacant, the control logic loads a first set of N instructions into the N consecutive storage elements. The control logic treats one or more of the storage elements occupied by the first set of N instructions as vacant storage elements dependent upon a position of a jump instruction in the first set of N instructions so that instructions can be shifted into the vacant storage elements.

Inventors: Schwendinger; Greg (Santa Clara, CA)

Assignee: Intel Corporation

International Classification: G06F 5/06 (20060101); G06F 9/38 (20060101); G06F 009/38 ()

Expiration Date: 06/26/2018