Patent Number: 6,251,564

Title: Method for forming a pattern with both logic-type and memory-type circuit

Abstract: A method for forming a pattern with both a logic-type and, a memory-type circuit is disclosed. The method includes first providing a wafer which includes a photoresist layer, then covering the photoresist layer with a first mask including an opaque area and a first pattern area. Forming a first pattern on the photoresist layer by a first exposure. Covering the photoresist layer with a second mask after the first mask is removed. Moreover, a second pattern is printed on the photoresist layer by a second exposure. Finally, the second mask is removed. The double-exposure method will enhance the resolution of the pattern defined on the photoresist layer.

Inventors: Lin; Chin-Lung (Kaohsiung, TW), Ku; Yao-Ching (Chiung-Lin Hsiang, TW)

Assignee: United Microelectronics Corp.

International Classification: G03F 7/20 (20060101); G03C 005/00 ()

Expiration Date: 06/26/2018