Patent Number: 6,251,693

Title: Semiconductor processing methods and semiconductor defect detection methods

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly-distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon-containing material.

Inventors: Nuttall; Michael (Meridian, ID), Mercaldi; Garry A. (Meridian, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/66 (20060101); H01L 021/66 (); G01R 031/26 ()

Expiration Date: 06/26/2018