Patent Number: 6,251,694

Title: Method of testing and packaging a semiconductor chip

Abstract: The present invention provides a method of testing and packaging a semiconductor chip. The semiconductor chip includes an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method includes using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer has an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.

Inventors: Liu; Hermen (Taoyuan, TW), Huang; Yimin (Tai-Chung Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 23/58 (20060101); H01L 21/66 (20060101); H01L 23/48 (20060101); H01L 23/485 (20060101); H01L 031/26 ()

Expiration Date: 06/26/2018