Patent Number: 6,251,695

Title: Multichip module packaging process for known good die burn-in

Abstract: A method of packaging and testing integrated circuit dies includes coupling a first integrated circuit to the substrate; encapsulating the first integrated circuit; and then testing the first integrated circuit. If testing is successful, a second integrated circuit is coupled to the substrate. In addition, the method may include encapsulating the second integrated circuit so that the first and second integrated circuits are part of a single monolithic module, such as a multichip module. The second integrated circuit may also be tested after encapsulation. The present invention may also be practiced by encapsulating and testing lesser value die before encapsulating higher value die. This reduces the chance that a higher value die will be rendered unusable because one of the lower value dies attached to the substrate is subsequently found defective after the higher value die has been encapsulated and/or tested.

Inventors: Kwon; Young I. (San Jose, CA)

Assignee: S3 Graphics Co., Ltd.

International Classification: H01L 23/28 (20060101); H01L 23/31 (20060101); H01L 21/66 (20060101); H01L 23/544 (20060101); H01L 021/66 ()

Expiration Date: 06/26/2018