Patent Number: 6,251,696

Title: Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate

Abstract: A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.

Inventors: Ikeya; Masahisa (Tokyo, JP), Inokuchi; Kazuyuki (Tokyo, JP)

Assignee: Oki Electric Industry, Co. Ltd.

International Classification: H01L 23/48 (20060101); H01L 23/544 (20060101); H01L 021/66 ()

Expiration Date: 06/26/2018