Patent Number: 6,251,704

Title: Method of manufacturing semiconductor devices having solder bumps with reduced cracks

Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.

Inventors: Ohuchi; Shinji (Tokyo, JP), Egawa; Yoshimi (Tokyo, JP), Anzai; Noritaka (Tokyo, JP)

Assignee: Oki Electric Industry Co., Ltd.

International Classification: H01L 21/02 (20060101); H01L 21/48 (20060101); H01L 23/498 (20060101); H01L 23/48 (20060101); H01L 21/60 (20060101); H05K 3/34 (20060101); H05K 3/40 (20060101); H01L 021/44 (); H01L 021/48 (); H01L 021/50 (); H01L 021/302 (); H01L 021/461 (); H01L 023/48 (); H01L 023/52 (); H01L 029/40 ()

Expiration Date: 06/26/2018