Patent Number: 6,251,705

Title: Low profile integrated circuit packages

Abstract: The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.

Inventors: Degani; Yinon (Highland Park, NJ), Dudderar; Thomas Dixon (Chatham, NJ), Tai; King Lien (Berkeley Heights, NJ)

Assignee: Agere Systems Inc.

International Classification: H01L 21/02 (20060101); H01L 21/60 (20060101); H01L 021/48 ()

Expiration Date: 06/26/2018