Patent Number: 6,251,710

Title: Method of making a dual damascene anti-fuse with via before wire

Abstract: An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said patterned anti-fuse material includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse material, wherein said patterned interlevel dielectric includes vias, as least one of said vias includes a via space; and a second level of electrically conductive features formed in said vias and via spaces.

Inventors: Radens; Carl J. (LaGrangeville, NY), Brintzinger; Axel C. (Fishkill, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 23/52 (20060101); H01L 23/525 (20060101); H01L 021/82 ()

Expiration Date: 06/26/2018