Patent Number: 6,251,716

Title: JFET structure and manufacture method for low on-resistance and low voltage application

Abstract: This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased. The normally on and normally off JFET transistors are configured to achieve low voltage drop, low on resistance, high current density and high frequency operations.

Inventors: Yu; Ho-Yuan (Saratoga, CA)

Assignee: Lovoltech, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/337 (20060101); H01L 29/66 (20060101); H01L 29/808 (20060101); H03K 17/06 (20060101); H01L 021/337 ()

Expiration Date: 06/26/2018