Patent Number: 6,251,719

Title: Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices

Abstract: A new method is provided for the creation of poly gate electrodes. A layer of poly-1 is deposited over the surface of a layer of ONO, a layer of TEOS-1 is deposited over the layer of poly-1. The layer of TEOS-1 is patterned in accordance with the pattern of the gate electrodes, the layer of poly-1 is dry etched using the patterned layer of TEOS-1 as a hard mask after which the layer of TEOS-1 forms a top IPO layer for the gate structure. A layer of silicon nitride is deposited over the pattern of gate electrodes, a layer of TEOS-2 is deposited over the surface of the layer of silicon nitride. The layer of TEOS-2 is etched applying a dry etch using the layer of silicon nitride as an etch stop thereby forming gate spacers on the sidewalls of the gate electrodes. The silicon nitride is next removed from the surface of the gate electrodes and from between the gate spacers by applying a silicon nitride wet etch. A buffer oxide etch (BOE) or HF wet dip removes the top oxide layer of the layer of ONO from between the gate spacers after which a layer of HTO is redeposited over the structure including the surface of the gate electrode (which is the exposed layer of TEOS-1), the gate spacers (formed of silicon nitride over which remains TEOS-2) and the opening that has been created in the layer of ONO. The layer of poly-2 is now deposited, completing the formation of the poly-1/poly-2 layers that from part of gate electrodes structures.

Inventors: Wang; Jen Pan (Tainan County, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/70 (20060101); H01L 21/8234 (20060101); H01L 27/148 (20060101); H01L 21/8242 (20060101); H01L 021/823 (); H01L 021/824 (); H01L 021/476 (); H01L 021/44 ()

Expiration Date: 06/26/2018