Patent Number: 6,251,721

Title: Semiconductor device and method of manufacturing the same

Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.

Inventors: Kanazawa; Kenichi (Kawasaki, JP), Hashimoto; Koichi (Kawasaki, JP), Takao; Yoshihiro (Kawasaki, JP), Katsube; Masaki (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/285 (20060101); H01L 21/60 (20060101); H01L 21/8242 (20060101); H01L 27/108 (20060101); H01L 021/824 (); H01L 021/20 (); H01L 021/476 ()

Expiration Date: 06/26/2018