Patent Number: 6,251,722

Title: Method of fabricating a trench capacitor

Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.

Inventors: Wei; Houng-chi (Yi Lan County, TW), Wang; Tso-chun Tony (Tai Chung, TW)

Assignee: Mosel Vitelic Inc.

International Classification: H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/824 ()

Expiration Date: 06/26/2018