Patent Number: 6,251,724

Title: Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity

Abstract: A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removing the silicon nitride, H.sub.2 can penetrate to the polysilicon and thereby increase the uniformity of the VT. In a first embodiment of the invention, the silicon nitride capacitor dielectric layer is etched away from over the poly-1 layer in the pad area. The removal of the SiN layer allows H.sub.2 to penetrate into the poly-1 layer and improve the threshold voltage (VT). Uniformity of long channel VT-N was improved when we modify the pad struture of PCM to increase the clear out ratio of capacitor Si.sub.3 N.sub.4 to 1.0584%. In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the process control monitor (PCM) testsite area between the chips. In a third embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the scribe area between the between the chips.

Inventors: Ku; Shu-Mei (Taipei County, TW), Wu; Lin-June (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 27/06 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/824 ()

Expiration Date: 06/26/2018