Patent Number: 6,251,725

Title: Method of fabricating a DRAM storage node on a semiconductor wafer

Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole. A second dry etching process is used to etch the second conductive layer using the photo resist layer as a mask so as to form the storage node. Finally, the photo resist layer is removed.

Inventors: Chiou; Jung-Chao (Hsin-Chu, TW), Wu; Te-Yuan (Hsin-Chu, TW), Wang; Chuan-Fu (Sanchung, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 21/8242 (20060101); H01L 021/824 ()

Expiration Date: 06/26/2018