Patent Number: 6,251,726

Title: Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar

Abstract: A method is provided for making capacitors for future high density circuits. The method increases capacitance while reducing the difficulty in etching the high aspect ratio holes for the capacitor node contacts. After FETs are formed in device areas, a first insulator is deposited and first contact openings are etched for the capacitor node contact. First polysilicon (polySi) plugs are formed in the first contact openings. An etch-stop layer and a second insulating layer are deposited. Second contact openings are aligned over and etched in the second insulating layer to the first polySi plugs. Second polySi plugs are formed in the second contact openings. Openings for capacitors, aligned over and wider than the second polySi plug, are etched in the second insulating layer. The capacitors are completed by forming bottom electrodes with a thin dielectric layer in the capacitor openings and forming a top electrode. This two polysi plug method reduces the need to etch a single high aspect ratio (deep) contacts holes. The second polysi plug also serves as a pillar for increased capacitance. The second contact openings and capacitor openings are etched using a very controllable etch to the etch-stop layer without disturbing the underlying DRAM structure. This allows capacitor design changes for future product generation beyond 0.25 um.

Inventors: Huang; Jenn Ming (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/336 ()

Expiration Date: 06/26/2018