Patent Number: 6,251,728

Title: Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Inventors: Patelmo; Matteo (Trezzo sull'Adda, IT), Galbiati; Nadia (Seregno, IT), Libera; Giovanna Dalla (Monza, IT), Vajana; Bruno (Bergamo, IT)

Assignee: STMicroelectronics S.r.l.

International Classification: H01L 21/70 (20060101); H01L 21/8234 (20060101); H01L 21/8247 (20060101); H01L 27/105 (20060101); H01L 021/336 ()

Expiration Date: 06/26/2018