Patent Number: 6,251,731

Title: Method for fabricating high-density and high-speed nand-type mask roms

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines. A high temperature annealing is carried out to form polycide in the word line regions, thereby finishing the fabrication.

Inventors: Wu; Shye-Lin (Hsinchu, TW)

Assignee: Acer Semiconductor Manufacturing, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/8234 (20060101); H01L 21/8246 (20060101); H01L 021/823 (); H01L 021/336 (); H01L 021/338 ()

Expiration Date: 06/26/2018