Patent Number: 6,251,733

Title: Semiconductor device and manufacturing method thereof

Abstract: In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors along the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those between the impurity regions in the p-channel transistor so as to make the absolute values of the threshold voltages of the n-channel and p-channel transistors approximately equal to each other. Where active layers are formed by utilizing a crystal structural body that is a collection of needle-like or columnar crystals, the same effect can be attained by controlling the width of the needle-like or columnar crystals.

Inventors: Yamazaki; Shunpei (Tokyo, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H01L 27/12 (20060101); H01L 27/085 (20060101); H01L 27/092 (20060101); H01L 021/336 (); H01L 021/00 ()

Expiration Date: 06/26/2018