Patent Number: 6,251,736

Title: Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Inventors: Brambilla; Claudio (Concorezzo, IT), Cereda; Sergio Manlio (Lomagna, IT), Caprara; Paolo (Milan, IT)

Assignee: STMicroelectronics S.r.l.

International Classification: H01L 21/70 (20060101); H01L 21/8247 (20060101); H01L 021/336 ()

Expiration Date: 06/26/2018