Patent Number: 6,251,737

Title: Method of increasing gate surface area for depositing silicide material

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Inventors: Lee; Tong-Hsin (Taipei Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/28 (20060101); H01L 29/423 (20060101); H01L 29/40 (20060101); H01L 021/336 ()

Expiration Date: 06/26/2018