Patent Number: 6,251,740

Title: Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit

Abstract: A vertical plate capacitor is formed in interlayer dielectric material which separates conductors of upper and lower interconnect layers by a method which avoids the accumulation of residual materials from chemical mechanical polishing (CMP). The method comprises the steps of forming a capacitor via into the interlayer dielectric material, forming a first conductive layer having a U-shaped portion into the capacitor via, forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer, forming a second conductive layer having a U-shaped portion in the U-shaped capacitor dielectric material, filling an interior of the U-shaped portion of the second conductive layer with a plug material, and polishing after the capacitor via is entirely occupied by these elements.

Inventors: Johnson; Gregory A. (Colorado Springs, CO), Taravade; Kunal N. (Colorado Springs, CO)

Assignee: LSI Logic Corporation

International Classification: H01L 21/02 (20060101); H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 23/522 (20060101); H01L 021/20 ()

Expiration Date: 06/26/2018