Patent Number: 6,251,741

Title: Method of manufacturing a semiconductor device

Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.

Inventors: Kinugasa; Akinori (Tokyo, JP), Mametani; Tomoharu (Tokyo, JP), Nagai; Yukihiro (Tokyo, JP), Nishimura; Hiroaki (Tokyo, JP), Kishida; Takeshi (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 27/108 (20060101); H01L 021/824 ()

Expiration Date: 06/26/2018