Patent Number: 6,251,745

Title: Two-dimensional scaling method for determining the overlay error and overlay process window for integrated circuits

Abstract: A novel two-dimensional scaling method is used to determine overlay errors on a pilot wafer for more accurate alignment when a photoresist is exposed in a step-and-repeat tool on product wafers. The method is useful for accurately aligning interconnections over contact holes in field (circuit) areas. A first photoresist layer is deposited on a pilot wafer having a planar insulating layer, and exposed through a first reticle that is stepped across the wafer to form contact holes in the array of field areas and first registration patterns adjacent to the field areas. Contact holes are etched and filled with metal. A conducting layer is deposited. A second photoresist layer is deposited and exposed through a second reticle to form an etch mask for interconnections and second registration patterns. During exposure, the interfield expansion parameter in the algorithm for the step-and-repeat tool is used to gradually shift the image from wafer center to wafer edge in both x and y directions. This 2-D scaling allows the overlay error between the interconnections and contact holes to be more accurately measured in each field area. The overlay error data provides registration pattern parameters used in the algorithm to improve alignment in the individual field areas on product wafers.

Inventors: Yu; Shinn-Sheng (Taichung, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/66 (20060101); H01L 23/544 (20060101); H01L 021/76 ()

Expiration Date: 06/26/2018