Patent Number: 6,251,746

Title: Methods of forming trench isolation regions having stress-reducing nitride layers therein

Abstract: Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.

Inventors: Hong; Soo-Jin (Seoul, KR), Yu; Yung-Seob (Kyunggi-do, KR), Koo; Bon-Young (Suwon, KR), Kim; Byung-Ki (Kyunggi-do, KR), Shin; Seung-Mok (Kyunggi-do, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 021/76 ()

Expiration Date: 06/26/2018